`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/06/23 00:17:03
// Design Name: 
// Module Name: HarpsTop
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:

//////////////////////////////////////////////////////////////////////////////////
module system_top   
(
 // Ôö¼Ó1ppsÐÅºÅ
    input i_pps,
 //SYSTEM
    input                   	sys_rst_i,
    input                   	sys_clk_p,
    input                   	sys_clk_n,
    //LOCAL
    output [3:0]             	led,
    output                  	clk_out,
//    output                   	pulse_o,
    inout                   	iic_scl,
    inout                   	iic_sda,
    
    output                      tx1_b_hmc624_spi_cs,   //by z
    output                    	tx1_hmc624_spi_cs,
    output                    	tx1_hmc624_spi_clk,
    output                    	tx1_hmc624_spi_data,
    
    output                      rx1_b_hmc624_spi_cs,  //by z
    output                    	rx1_hmc624_spi_cs,
    output                    	rx1_hmc624_spi_clk,
    output                    	rx1_hmc624_spi_data,
    //PCIE
    output [14:0]				DDR3_addr,
    output [2:0]				DDR3_ba,
    output 						DDR3_cas_n,
    output [0:0]				DDR3_ck_n,
    output [0:0]				DDR3_ck_p,
    output [0:0]				DDR3_cke,
    output [0:0]				DDR3_cs_n,
    output [3:0]				DDR3_dm,
    inout  [31:0]				DDR3_dq,
    inout  [3:0]				DDR3_dqs_n,
    inout  [3:0]				DDR3_dqs_p,
    output [0:0]				DDR3_odt,
    output 						DDR3_ras_n,
    output 						DDR3_reset_n,
    output 						DDR3_we_n,
 //   output 						o_wr_int,
 //    output 						o_rd_int,
    
    input  [3:0]				pcie_mgt_rxn,
    input  [3:0]				pcie_mgt_rxp,
    output [3:0]				pcie_mgt_txn,
    output [3:0]				pcie_mgt_txp,
    input   					pcie_rst_n,
    input  [0:0]				pcie_ref_clk_n,
    input  [0:0]				pcie_ref_clk_p,
    //ZYNQ PS Interface
    inout   [14:0]          	ddr_addr    ,        
    inout   [ 2:0]          	ddr_ba      ,
    inout                   	ddr_cas_n   ,
    inout                   	ddr_ck_n    ,
    inout                   	ddr_ck_p    ,
    inout                   	ddr_cke     ,
    inout                   	ddr_cs_n    ,
    inout   [ 3:0]          	ddr_dm      ,
    inout   [31:0]          	ddr_dq      ,
    inout   [ 3:0]          	ddr_dqs_n   ,
    inout   [ 3:0]          	ddr_dqs_p   ,
    inout                   	ddr_odt     ,
    inout                   	ddr_ras_n   ,
    inout                   	ddr_reset_n ,
    inout                   	ddr_we_n    ,
						
    inout                   	fixed_io_ddr_vrn ,
    inout                   	fixed_io_ddr_vrp ,
    inout   [53:0]          	fixed_io_mio     ,
    inout                   	fixed_io_ps_clk  ,
    inout                   	fixed_io_ps_porb ,
    inout                   	fixed_io_ps_srstb,
    
    //AD9361_0 Interface by z
    input                   	rx_clk_in_0_p,
    input                   	rx_clk_in_0_n,
    input                   	rx_frame_in_0_p,
    input                   	rx_frame_in_0_n,
    input   [ 5:0]      		rx_data_in_0_p,
    input   [ 5:0]      		rx_data_in_0_n,
		
    output                  	tx_clk_out_0_p,
    output                  	tx_clk_out_0_n,
    output                  	tx_frame_out_0_p,
    output                  	tx_frame_out_0_n,
    output  [ 5:0]      		tx_data_out_0_p,
    output  [ 5:0]      		tx_data_out_0_n,

    inout       [ 7:0]          gpio_status_0,
    inout       [ 3:0]          gpio_ctl_0,
    inout                       gpio_en_agc_0,
    output      reg             mcs_sync,
    inout                       gpio_resetb_0,   //by z
    output                      enable_0,
    output                      txnrx_0,
    
    //AD9361_1 Interface by z
    input                   rx_clk_in_1_p,
    input                   rx_clk_in_1_n,
    input                   rx_frame_in_1_p,
    input                   rx_frame_in_1_n,
    input       [ 5:0]      rx_data_in_1_p,
    input       [ 5:0]      rx_data_in_1_n,
    output                  tx_clk_out_1_p,
    output                  tx_clk_out_1_n,
    output                  tx_frame_out_1_p,
    output                  tx_frame_out_1_n,
    output      [ 5:0]      tx_data_out_1_p,
    output      [ 5:0]      tx_data_out_1_n,
    inout       [ 7:0]      gpio_status_1,
    inout       [ 3:0]      gpio_ctl_1,
    inout                   gpio_en_agc_1,
    inout                   gpio_resetb_1,   //by z
    output                  enable_1,
    output                  txnrx_1,
    
	
	//gpio	
   
       
    inout       [ 14:0]         gpio_bd,
    
    //by z inout                    	spi_csn,
   
    output                  spi_ad9361_0,  //by z
    output                  spi_ad9361_1,  //by z
  //output                  spi_ad5355,by z//by z
    output                  spi_clk,   //by z
    output                  spi_mosi,  //by z
    input                   spi_miso,  //by z
    
    // output                   	validref,
    // output                   	SwitchOutput,
//   output                   	tx1_dat,
//   input                    	rx1_dat,    //���Ÿ�LEDʹ��
    input                       ref_clk_p,   //by z    
    
    output                      PPS1,       
    output                      PPS2,        //by fcm      
    output                      LED_system,        //by fcm    
    output                      LED_master,        //by fcm    
    output                      LED_slave,        //by fcm    
    output                      LED_sync
    );
    
     wire    [ 2:0]  spi0_csn;//by z
     wire            spi0_clk;//by z
     wire            spi0_mosi;
     wire            spi0_miso;
     wire    [ 2:0]  spi1_csn;
     wire            spi1_clk;
      wire           spi1_mosi;
     wire            spi1_miso;
     
        
     
  //   assign mcs_sync = 1'd0;
     
    //================ clock and reset manager
    wire sys_clk_200M,Local_Clk_200M,Local_Clk_40_92M,Local_Clk_50M,Local_Clk_10M,Local_Clk_10_23M;
	reg     [31:0]              sys_rstn_reg;
    reg                         sys_rstn;
    wire                        hard_reset_n;
    Clk_Dif2Sig Clk_Dif2Sig
    (
    .i_clk_p(sys_clk_p),
    .i_clk_n(sys_clk_n),
    .o_clk(sys_clk_200M)
    );
    
    Local_Clk_Gen Local_Clk_Gen
    (
    .clk_out_200M(Local_Clk_200M),
    .clk_out_100M(Local_Clk_40_92M),
    .clk_out_50M(Local_Clk_50M), 
    .clk_out_10M(Local_Clk_10M), 
    .clk_out_5M(Local_Clk_10_23M), 
    .clk_in1(sys_clk_200M)
    );
    always@( posedge Local_Clk_50M or negedge sys_rst_i)begin
        if( !sys_rst_i )begin
            sys_rstn_reg    <=    32'd0;
            sys_rstn        <=    1'b0;
        end
        else begin
            sys_rstn_reg    <=  {sys_rstn_reg[30:0],1'b1};
            sys_rstn        <=   sys_rstn_reg[31];    
        end
    end       
    
    assign    hard_reset_n = sys_rstn;
    assign    clk_out = sys_clk_200M;       
     
    //==================ps
 //   wire                PS_FCLK0;
    wire                PS_FRSTN0;
    wire    [31:0]      adi_mrd32_addr; 
    wire    [31:0]      adi_mrd32_data; 
    wire                adi_mrd32_rden; 
    wire    [31:0]      adi_mwr32_addr; 
    wire    [31:0]      adi_mwr32_data; 
    wire                adi_mwr32_wren; 

    wire    [31:0]      rx1_att;
    wire    [31:0]      tx1_att;
    

    wire    [31:0]      rx1_b_att; // by z
    wire    [31:0]      tx1_b_att; // by z  
    
    wire    [63:0]  	gpio_i;
    wire    [63:0]      gpio_o;
    wire    [63:0]      gpio_t;
    wire                pcie_lnk_up; 
    wire                ddr_initdone;
    wire    [11:0]      device_temp; 
    wire    [3:0]       hw_status ;
    
    wire                DDS_en;
    wire                FPGA_GenCodeEnable;
    wire                ad9361_initdone ;
    wire                ad9361_pll_lock;   
    wire                fir_en; 
    wire                data_clk_ce;    
   
  //gpio output init(trnrx¡¢enable¡¢agc¡¢reset)  by z  
    wire          gpio_txnrx_1;           
    wire          gpio_enable_1;         
  
    wire          gpio_txnrx_0;           
    wire          gpio_enable_0;         
    
    assign        gpio_en_agc_0 = 0 ;     
    assign        gpio_en_agc_1 = 0 ;     // by z
    
  
    assign        gpio_txnrx_1 =  sys_rstn;  
    assign        gpio_enable_1 = 0;          
    assign        gpio_txnrx_0  = sys_rstn;
    assign        gpio_enable_0 = 0;  
    
     

    ad_iobuf #(
    .DATA_WIDTH(32)//(57)//by z
  ) i_iobuf (
  
       .dio_t ({gpio_t[47:16]}),//by z
       .dio_i ({gpio_o[47:16]}),//by z
       .dio_o ({gpio_i[47:16]}), //by z
       .dio_p ({

              gpio_resetb_1,          // 47  by z
              gpio_resetb_0,          // 46
              ad9361_initdone,        // 45 by z
              ad9361_pll_lock,        // 44 by z
              DDS_en,      // 43   by z Ã»³õÊ¼»¯
              FPGA_GenCodeEnable,     // 42
              data_clk_ce,            // 41  by z
              fir_en,                 // 40   by z
              gpio_ctl_1,             // 39:36
              gpio_ctl_0,             // 35:32
              gpio_status_1,          // 31:24
              gpio_status_0}));       // 23:16
          //by z    gpio_bd}));       // 14: 0
          
    assign  hw_status[0] = data_clk_ce;//ad9361_initdone & ad9361_pll_lock;
    assign  hw_status[1] = pcie_lnk_up;
    assign  hw_status[2] = ddr_initdone;
    assign  hw_status[3] = 1;
    
    
    //-----------------------------
    wire                data_clk;
    wire                data_clk_ibuf;
    
     BUFGCE BUFGCE_data_clk_inst (
      .O(data_clk),   // 1-bit output: Clock output
      .CE(FPGA_GenCodeEnable),//data_clk_ce), // 1-bit input: Clock enable input for I0  by z
      .I(data_clk_ibuf)    // 1-bit input: Primary clock
   );
    
    
    
    
    
    
    //--------------   
    
 
 wire tx1_hmc624_spi_data_sw;
 wire tx1_hmc624_spi_clk_sw;
 
 wire rx1_hmc624_spi_data_sw;
 wire rx1_hmc624_spi_clk_sw;
 
 wire tx1_b_hmc624_spi_data_sw;
 wire tx1_b_hmc624_spi_clk_sw;
 
 wire rx1_b_hmc624_spi_data_sw;
 wire rx1_b_hmc624_spi_clk_sw;
 
hmc624_SPI i_tx1_attn
    (        
        .Reset              (!hard_reset_n          ),
        .Sys_clk            (Local_Clk_10M          ),
        .att_data           (tx1_att[5:0]                ),
        .SSEN               (tx1_hmc624_spi_cs      ),
        .SCK                (tx1_hmc624_spi_clk_sw     ),
        .MOSI               (tx1_hmc624_spi_data_sw)
    );       

//by z    
hmc624_SPI i_tx1_b_attn
    (        
        .Reset              (!hard_reset_n          ),
        .Sys_clk            (Local_Clk_10M          ),
        .att_data           (tx1_b_att[5:0]                ),
        .SSEN               (tx1_b_hmc624_spi_cs      ),
        .SCK                (tx1_b_hmc624_spi_clk_sw     ),
        .MOSI               (tx1_b_hmc624_spi_data_sw)
    );   
          
hmc624_SPI i_rx1_attn
    (        
        .Reset              (!hard_reset_n          ),
        .Sys_clk            (Local_Clk_10M          ),
        .att_data           (rx1_att[5:0]                ),
        .SSEN               (rx1_hmc624_spi_cs      ),
        .SCK                (rx1_hmc624_spi_clk_sw     ),
        .MOSI               (rx1_hmc624_spi_data_sw)
    );
    
// by z    
hmc624_SPI i_rx1_b_attn
    (        
        .Reset              (!hard_reset_n          ),
        .Sys_clk            (Local_Clk_10M          ),
        .att_data           (rx1_b_att[5:0]                ),
        .SSEN               (rx1_b_hmc624_spi_cs      ),
        .SCK                (rx1_b_hmc624_spi_clk_sw     ),
        .MOSI               (rx1_b_hmc624_spi_data_sw)
    );
    
    assign rx1_hmc624_spi_clk  = !rx1_b_hmc624_spi_cs ?  rx1_b_hmc624_spi_clk_sw  : rx1_hmc624_spi_clk_sw; 
    assign rx1_hmc624_spi_data = !rx1_b_hmc624_spi_cs ?  rx1_b_hmc624_spi_data_sw : rx1_hmc624_spi_data_sw;
    
    assign tx1_hmc624_spi_clk  = !tx1_b_hmc624_spi_cs ?  tx1_b_hmc624_spi_clk_sw  : tx1_hmc624_spi_clk_sw; 
    assign tx1_hmc624_spi_data = !tx1_b_hmc624_spi_cs ?  tx1_b_hmc624_spi_data_sw : tx1_hmc624_spi_data_sw;
    
    
    
//======================================
wire [12:0]BRAM_PORTA_addr;
wire BRAM_PORTA_clk;
wire [31:0]BRAM_PORTA_din;
wire [31:0]BRAM_PORTA_dout;
wire BRAM_PORTA_en;
wire BRAM_PORTA_rst;
wire [3:0]BRAM_PORTA_we;  
wire   TX2Enable;
wire   TX2Enable_TX;   //by z
wire 	[31:0] 		seg_need_read;
wire 	[31:0] 		seg_need_write;
wire 	[31:0] 		seg_need_read_GNSS_PPS;
wire 	[31:0] 		seg_need_read_Delay_cnt;
wire    [31:0]      PPS_control_back;
wire    [31:0]      PPS_control;
wire    [31:0]      DAC_cnt_reset_val;
wire    [31:0]      LED_Val;
pcie_lite_map pcie_lite_map
    (
    .bramctrl_clk           (BRAM_PORTA_clk     ),
    .bramctrl_rst           (BRAM_PORTA_rst     ),
    .bramctrl_addr          (BRAM_PORTA_addr    ),
    .bramctrl_data_out      (BRAM_PORTA_din     ),
    .bramctrl_we            (BRAM_PORTA_we      ),
    .bramctrl_en            (BRAM_PORTA_en      ),
    .bramctrl_data_in       (BRAM_PORTA_dout    ),
	//user
    .seg_need_read          (seg_need_read      ),
    .seg_need_write         (seg_need_write     ),
    .seg_need_read_GNSS_PPS (seg_need_read_GNSS_PPS),
    .seg_need_read_Delay_cnt(seg_need_read_Delay_cnt),
    .PPS_control_back       (PPS_control_back),
    .TX2Enable              (TX2Enable          ),
    .TX2Enable_TX           (TX2Enable_TX       ),
    .TestRegIn              (),
    .TestRegOut             (PPS_control),
    .DAC_cnt_reset_val      (DAC_cnt_reset_val),
    .LED_Val                (LED_Val)
    );

LED_Control LED_Control_u(
   .bramctrl_clk(BRAM_PORTA_clk),
   .bramctrl_rst(BRAM_PORTA_rst),
   .bramctrl_val(LED_Val),
   .LED_system(LED_system),        //by fcm    
   .LED_master(LED_master),        //by fcm    
   .LED_slave(LED_slave),        //by fcm    
   .LED_sync(LED_sync)
);
wire                pcie_clk_200M;
wire                fdma_rstn;
wire[4:0]           idly_d;
wire[6:0]           idly_en;     
wire                adc_status;

wire                ap_rst_n;
wire                 dac_valid;
reg [11:0]          dac_data_i1;
reg [11:0]          dac_data_q1;
reg [11:0]          dac_data_i2;
reg [11:0]          dac_data_q2;
wire                adc_valid;
wire [11:0]         adc_data_i1;
wire [11:0]	        adc_data_q1;
wire [11:0]         adc_data_i2;
wire [11:0]	        adc_data_q2; 


//================================================
wire [31:0]pkg_rd_addr,pkg_rd_size;
wire [127:0]pkg_rd_data;
wire pkg_rd_areq,pkg_rd_en,pkg_rd_last;

(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) wire [31:0]pkg_wr_addr,pkg_wr_size;
(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) wire [127:0]pkg_wr_data;
(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) wire pkg_wr_areq,pkg_wr_en,pkg_wr_last;
(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) wire [1:0]usr_irq_req;
wire ui_clk,ReadReqInt,WriteReqInt;
// assign o_wr_int = WriteReqInt;
// assign o_rd_int = ReadReqInt;
assign usr_irq_req = {ReadReqInt,WriteReqInt};
//-------------------------------------------------------------------------------------------------------------------------------------------
//------------------code for sim
reg[1:0]         SampClkCnt; 
wire Code_Shift_Flag;
wire mod_code;
always@(posedge data_clk)begin
    if(!hard_reset_n)SampClkCnt<=0;
    else begin
        SampClkCnt<=SampClkCnt+1;
    end
end
assign Code_Shift_Flag = (SampClkCnt==3)?1:0;
 sim_code_gen sim_code_gen(
    .sclk(data_clk),
	.rst_n(hard_reset_n),
	.PRN_num(1),
	.Code_Shift_Flag(Code_Shift_Flag),
	.pn_code(mod_code)
	); 
//	); 
	  
//-------------------------
  



 reg sensor_rd_req;

 wire [63:0]sensor_rd_data;   // for 40M TX 40M RX(single AD9364)
 reg [63:0]dac_data_0;


 wire  dac_valid_local;
 wire  dac_fifo_underflow;
 reg [1:0]dac_valid_cnt;

reg [1:0]dac_valid_cnt_n;

 reg  dac_axi_valid;

 wire   dac_axi_ready;


 
always @(negedge data_clk)begin
    if(!fdma_rstn) dac_valid_cnt_n<= 0;
 
   else if(dac_valid_local==1 && dac_fifo_underflow==0  ) dac_valid_cnt_n<=dac_valid_cnt_n+1;
end




always @(posedge data_clk)begin

    if(!fdma_rstn)sensor_rd_req<=0;
    else begin
        if(dac_valid_cnt_n==3)sensor_rd_req<=1;
     
        else sensor_rd_req<=0;
    end
end    




always @(posedge data_clk)begin

  
  

 if(TX2Enable_TX==0)
         begin
             dac_data_0[63:0] <= 64'd0;      
         end
 else begin   


  
          case(dac_valid_cnt_n)
                 

       
       
            2'b01:begin   dac_data_0[63:0] <=  {16'h0000,16'h0000,sensor_rd_data[15:8], 8'd0,sensor_rd_data[7:0],8'd0};          end
            2'b10:begin   dac_data_0[63:0] <=  {16'h0000,16'h0000,sensor_rd_data[31:24], 8'd0,sensor_rd_data[23:16],8'd0};       end
            2'b11:begin   dac_data_0[63:0] <=  {16'h0000,16'h0000,sensor_rd_data[47:40], 8'd0,sensor_rd_data[39:32],8'd0};       end
            2'b00:begin   dac_data_0[63:0] <=  {16'h0000,16'h0000,sensor_rd_data[63:56], 8'd0,sensor_rd_data[55:48],8'd0};       end 
       
       
       
       
                    
                       
           endcase   
 
        end
  end
  
  
         
 





//------------------------
 wire [63:0] sensor_wr_data_pps;  //for pps
 wire [63:0] sensor_wr_data_pps_copy;  //for pps
(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) reg sensor_wr_req;


(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) reg [15:0]sensor_wr_data; //[63:0]

(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) reg [7:0]adc_i_data; 
(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) reg [7:0]adc_q_data; 

(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *)reg [7:0]adc_i_data_div; 
(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) reg [7:0]adc_q_data_div; 

(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) wire  [63:0] adc_data_0;
(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *)wire adc_packed_fifo_wr_sync;//by z
wire   sensor_W0_wr_full;//by z

(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) reg adc_valid_cnt;  //for 20 rx


//----------------------------

//always @(posedge data_clk)begin
//    adc_i_data_div <= sensor_wr_data[7:0] ;
//    adc_q_data_div <= sensor_wr_data[15:8] ;
// end



//--------------------------
always @(posedge data_clk)begin
  if(!fdma_rstn && adc_packed_fifo_wr_sync) adc_valid_cnt<=0;  //by z

   
    else if(adc_valid) adc_valid_cnt<=adc_valid_cnt+1;
end

always @(posedge data_clk)begin
   if(!fdma_rstn)sensor_wr_req<=0;

    else begin




     
          sensor_wr_req<=adc_valid;     //for 40 rx

    end
 end

always @(negedge data_clk)begin    //***posedge
    if(adc_valid==1)begin
                
               sensor_wr_data[7:0]  <=adc_data_0[11:4];  
               sensor_wr_data[15:8] <=adc_data_0[27:20];
                               
               end
end

//--------------------for 1pps
wire PPS_ref_IN;
wire PPS_local_IN;

wire [64-1:0]data_pps;
wire m_data_pps,sensor_wr_req_pps;

data_cpkg				i_ddc_cpkg
(
	.sys_clk_i			(data_clk			),
	.sys_rst_i      	(~hard_reset_n	),								
	.ddc0_data       	(sensor_wr_data	),
	.ddc0_valid      	(sensor_wr_req	),
	.pkg_data       	(sensor_wr_data_pps  	),
    .pkg_data_copy      (sensor_wr_data_pps_copy  	),
	.GNSS_pps           (i_pps),
    .PPS_local_IN       (PPS_local_IN),    
	.pkg_valid      	(sensor_wr_req_pps),
	.data_pps            (data_pps)

);



//----------------
fdma_controller fdma_controller
    (
    
//----------------add 1pps

    .i_data_pps          (data_pps),
//----------------------------------------------
    
    .i_ui_clk               (ui_clk             ),//100M  Fr DDR
    .i_ui_rstn              (fdma_rstn&TX2Enable),
    .i_sensor_wr_clk        (data_clk           ),  //clk_40M 40M Fr 9361
    .i_sensor_wr_en         (sensor_wr_req_pps     ),//(sensor_wr_req),   //9361å†™fifoä½¿èƒ½ä¿¡å·ï¼Œä¸€ç�?�´æ�?��?�é�??  for pps
    .i_sensor_wr_data       (sensor_wr_data_pps     ),//(sensor_wr_data), //sensor_wr_data  data Fr 9361  for pps ÓÉ16Î»¸ÄÎª64Î»
    .i_sensor_wr_data_copy    (sensor_wr_data_pps_copy),
    .W0_wr_full             (sensor_W0_wr_full     ),//by z
    .o_burst_wr_areq        (pkg_wr_areq        ),
    .i_burst_wr_en          (pkg_wr_en          ),
    .i_burst_wr_last        (pkg_wr_last        ),
    .o_burst_wr_addr        (pkg_wr_addr        ),
    .o_burst_wr_data        (pkg_wr_data        ),
    .o_burst_wr_size        (pkg_wr_size        ),
    .i_sensor_rd_clk        (data_clk           ), //clk_40M 40M Fr 9361
    .i_sensor_rd_en         (sensor_rd_req      ),  //(1),// 1 9361å†™fifoä½¿èƒ½ä¿¡å·ï¼Œä¸€ç�?�´æ�?��?�é�??
    .o_sensor_rd_data       (sensor_rd_data     ),//data To 9361 
    .o_burst_rd_areq        (pkg_rd_areq        ),       
    .i_burst_rd_en          (pkg_rd_en          ),
    .i_burst_rd_last        (pkg_rd_last        ),
    .o_burst_rd_addr        (pkg_rd_addr        ),
    .i_burst_rd_data        (pkg_rd_data        ),
    .o_burst_rd_size        (pkg_rd_size        ),
    .o_ReadReqInt           (ReadReqInt         ),      
    .o_WriteReqInt          (WriteReqInt        ),
    .dac_fifo_valid         (dac_valid_local        ),   //by z
    .dac_fifo_underflow         (dac_fifo_underflow),//by z
    .o_NeedReadSeg          (seg_need_read      ),    //SegNum: 1  2
    .o_NeedWriteSeg         (seg_need_write     ),    //SegNum: 1  2
    .o_NeedReadSegGNSS_PPS  (seg_need_read_GNSS_PPS)
    );


wire FCLK0_OUT;

// PPS_local_out比PPS_local慢一�?????
// TimeSync  TimeSync_inst(
//     .sys_clk(FCLK0_OUT),
//     .ADC_CLK(data_clk),
//     .rst_n(sys_rstn),
//     .control_offset(tx1_b_att),
//     .PPS_ref(PPS_ref_IN),
//     .PPS_local(PPS_local_IN),
//     .PPS_ref_out(PPS1),
//     .PPS_local_out(PPS2)
// );
// 

wire [31:0] PPS_ref_cnt;
TimeSync2  TimeSync_inst(
    .sys_clk(BRAM_PORTA_clk),
    .ADC_CLK(data_clk),
    .rst_n(sys_rstn),
    .control_offset(PPS_control),
    .control_offset_back(PPS_control_back),
    .PPS_ref_cnt(PPS_ref_cnt),
    .PPS_ref(PPS_ref_IN),
    .PPS_ref_out(PPS1),
    .PPS_local(PPS_local_IN),
    .PPS_local_out(PPS2)
);

(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) wire [31:0]tx1_att;
(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) wire [31:0]rx1_att;
(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) wire [31:0]rx1_b_att;
(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) wire [31:0]tx1_b_att;

// for Delay calculation
reg DAC_MARK;
always @(posedge data_clk)begin
    if(TX2Enable_TX==0)
        DAC_MARK    <= 1'b0;
    else if(dac_data_0[63:0]==64'h00000000FF00FF00) begin
        DAC_MARK    <= 1'b1;
    end
    else
        DAC_MARK    <= 1'b0;
end

DAC_Delay_PPS Delay_inst(
    .ADC_CLK(data_clk),
    .BRAM_PORTA_clk(BRAM_PORTA_clk),
    .rst_n(sys_rstn),
    .PPS_ref_cnt(PPS_ref_cnt),
    .DAC_MARK(DAC_MARK),
    .reset_val(DAC_cnt_reset_val),
    .Delay_cnt(seg_need_read_Delay_cnt)
    );

pcie_system_wrapper pcie_system_wrapper
       (      
        
        
        .enable_0(enable_0),
        .enable_1(enable_1),

      
        . s_axis_ready_0(dac_axi_ready),
        .dac_data_0(dac_data_0),
        
        .dac_valid_0(dac_valid_local),//dac_axi_valid),  //

        .packed_fifo_wr_data_0(adc_data_0),//(adc_data_pack),
        .packed_fifo_wr_en_0(adc_valid),
        .packed_fifo_wr_overflow_0(sensor_W0_wr_full),  //.packed_fifo_wr_overflow_0(0), by z
        .packed_fifo_wr_sync_0(adc_packed_fifo_wr_sync),

        .peripheral_aresetn_0_0(),

        
        .rx_clk_in_n_0(rx_clk_in_0_n),
        .rx_clk_in_n_1(rx_clk_in_1_n),
        .rx_clk_in_p_0(rx_clk_in_0_p),
        .rx_clk_in_p_1(rx_clk_in_1_p),
        .rx_data_in_n_0(rx_data_in_0_n),
        .rx_data_in_n_1(rx_data_in_1_n),
        .rx_data_in_p_0(rx_data_in_0_p),
        .rx_data_in_p_1(rx_data_in_1_p),
        .rx_frame_in_n_0(rx_frame_in_0_n),
        .rx_frame_in_n_1(rx_frame_in_1_n),
        .rx_frame_in_p_0(rx_frame_in_0_p),
        .rx_frame_in_p_1(rx_frame_in_1_p),

        
        .tx_clk_out_n_0(tx_clk_out_0_n),
        .tx_clk_out_n_1(tx_clk_out_1_n),
        .tx_clk_out_p_0(tx_clk_out_0_p),
        .tx_clk_out_p_1(tx_clk_out_1_p),
        .tx_data_out_n_0(tx_data_out_0_n),
        .tx_data_out_n_1(tx_data_out_1_n),
        .tx_data_out_p_0(tx_data_out_0_p),
        .tx_data_out_p_1(tx_data_out_1_p),
        .tx_frame_out_n_0(tx_frame_out_0_n),
        .tx_frame_out_n_1(tx_frame_out_1_n),
        .tx_frame_out_p_0(tx_frame_out_0_p),
        .tx_frame_out_p_1(tx_frame_out_1_p),
        .txnrx_0(txnrx_0),
        .txnrx_1(txnrx_1),
     
        .up_enable_0(gpio_enable_0),
        .up_enable_1(gpio_enable_1),
        .up_txnrx_0(gpio_txnrx_0),
        .up_txnrx_1(gpio_txnrx_1),
        
        .DDR3_addr(DDR3_addr),
        .DDR3_ba(DDR3_ba),
        .DDR3_cas_n(DDR3_cas_n),
        .DDR3_ck_n(DDR3_ck_n),
        .DDR3_ck_p(DDR3_ck_p),
        .DDR3_cke(DDR3_cke),
        .DDR3_cs_n(DDR3_cs_n),
        .DDR3_dm(DDR3_dm),
        .DDR3_dq(DDR3_dq),
        .DDR3_dqs_n(DDR3_dqs_n),
        .DDR3_dqs_p(DDR3_dqs_p),
        .DDR3_odt(DDR3_odt),
        .DDR3_ras_n(DDR3_ras_n),
        .DDR3_reset_n(DDR3_reset_n),
        .DDR3_we_n(DDR3_we_n),
        .init_calib_complete(ddr_initdone),    //by z
        .BRAM_PORTA_addr(BRAM_PORTA_addr),
        .BRAM_PORTA_clk(BRAM_PORTA_clk),
        .BRAM_PORTA_din(BRAM_PORTA_din),
        .BRAM_PORTA_dout(BRAM_PORTA_dout),
        .BRAM_PORTA_en(BRAM_PORTA_en),
        .BRAM_PORTA_rst(BRAM_PORTA_rst),
        .BRAM_PORTA_we(BRAM_PORTA_we),
        .clk_100M(),//acturally 40M by z
        .fdma_rstn(fdma_rstn),
        .user_lnk_up(pcie_lnk_up), //by z
        .usr_irq_req_0(usr_irq_req),//by z
 
        .pcie_mgt_rxn(pcie_mgt_rxn),
        .pcie_mgt_rxp(pcie_mgt_rxp),
        .pcie_mgt_txn(pcie_mgt_txn),
        .pcie_mgt_txp(pcie_mgt_txp),
        .pcie_ref_clk_n(pcie_ref_clk_n),
        .pcie_ref_clk_p(pcie_ref_clk_p),
        .pcie_rst_n(pcie_rst_n),
 
 
        .pkg_rd_addr(pkg_rd_addr),
        .pkg_rd_areq(pkg_rd_areq),
        .pkg_rd_data(pkg_rd_data),
        .pkg_rd_en(pkg_rd_en),
        .pkg_rd_last(pkg_rd_last),
        .pkg_rd_size(pkg_rd_size),
        .pkg_wr_addr(pkg_wr_addr),
        .pkg_wr_areq(pkg_wr_areq),
        .pkg_wr_data(pkg_wr_data),
        .pkg_wr_en(pkg_wr_en),
        .pkg_wr_last(pkg_wr_last),
        .pkg_wr_size(pkg_wr_size),
 
        .ui_clk(ui_clk),
 
        .clk_out_0(data_clk_ibuf),//clk_out_0),

        
        
        .DDR_addr 				(ddr_addr			),
        .DDR_ba                 (ddr_ba            	),
        .DDR_cas_n              (ddr_cas_n        	),
        .DDR_ck_n               (ddr_ck_n        	),
        .DDR_ck_p               (ddr_ck_p        	),
        .DDR_cke                (ddr_cke        	),
        .DDR_cs_n               (ddr_cs_n        	),
        .DDR_dm                 (ddr_dm            	),
        .DDR_dq                 (ddr_dq            	),
        .DDR_dqs_n              (ddr_dqs_n        	),
        .DDR_dqs_p              (ddr_dqs_p        	),
        .DDR_odt                (ddr_odt        	),
        .DDR_ras_n              (ddr_ras_n        	),
        .DDR_reset_n            (ddr_reset_n    	),
        .FCLK0_OUT              (FCLK0_OUT          ),
 
        .FIXED_IO_ddr_vrn       (fixed_io_ddr_vrn 	),
        .FIXED_IO_ddr_vrp       (fixed_io_ddr_vrp 	),
        .FIXED_IO_mio           (fixed_io_mio      	),
        .FIXED_IO_ps_clk        (fixed_io_ps_clk  	),
        .FIXED_IO_ps_porb       (fixed_io_ps_porb 	),
        .FIXED_IO_ps_srstb      (fixed_io_ps_srstb	),
  
        .GPIO_I(gpio_i[63:00]),//by z
        .GPIO_O(gpio_o[63:00]),//by z
        .GPIO_T(gpio_t[63:00]),//by z
 
    
              
        .SPI0_MISO_I_0(spi0_miso),
        .SPI0_MOSI_I_0(spi0_mosi),
        .SPI0_MOSI_O_0(spi0_mosi),
        .SPI0_SCLK_I_0(spi0_clk),
        .SPI0_SCLK_O_0(spi0_clk),
        .SPI0_SS1_O_0(spi0_csn[1]),
        .SPI0_SS2_O_0(spi0_csn[2]),
        .SPI0_SS_I_0(1'b1),
        .SPI0_SS_O_0(spi0_csn[0]),
         
//        .UART_1_0_rxd(rx1_dat), //by z
//        .UART_1_0_txd(tx1_dat), //by z
        .IIC_scl_io             (iic_scl        	), //by z
        .IIC_sda_io             (iic_sda        	), // by z

   //     .PS_FCLK0(PS_FCLK0),
        .PS_FRSTN0(PS_FRSTN0),    
        .temp_out(device_temp),//by z
        .idly_d_0(idly_d),    //by z
        .idly_en_0(idly_en),   //by z 
        .tx1_atten_0(tx1_att), //by z
        .rx1_atten_0(rx1_att), //by z
        
        .rx1_b_atten_0(rx1_b_att), //by z
        .tx1_b_atten_0(tx1_b_att), //by z
        
        .clk_200M(pcie_clk_200M)//by z
 
        );
    //==================gpio ctrl from ps
   
    
    assign spi_ad9361_0 = spi0_csn[0];
    assign spi_ad9361_1 = spi0_csn[1];
    //assign spi_ad5355   = spi0_csn[2];by z
    assign spi_clk = spi0_clk;
    assign spi_mosi = spi0_mosi;
    assign spi0_miso = spi_miso; 

      
          
          

led_bling i_led_bling
(
	.clk                    (Local_Clk_50M      ),
 	.rst                    (~hard_reset_n      ),
	.ena                    (hw_status          ),
 	.led                    (led                )
 );



endmodule